The present invention relates to a semiconductor memory device with such a structure as changing a potential level in the channel region of a field effect transistor (FET) by utilizing the hysteresis properties of a ferroelectric film.
An FET, called xe2x80x9cMFISFETxe2x80x9d, xe2x80x9cMFSFETxe2x80x9d or xe2x80x9cMFMISFETxe2x80x9d, has been known as a semiconductor memory device including a non-volatile storage section with a ferroelectric thin film in its gate. An FET with such a structure will be herein called a xe2x80x9cferroelectric FETxe2x80x9d.
FIG. 8 is a cross-sectional view of a known ferroelectric FET implemented as an MFISFET. As shown in FIG. 8, the FET includes silicon substrate 101, silicon dioxide (SiO2) film 102, ferroelectric film 103, gate electrode 104 and source/drain regions 105 and 106. The SiO2 film 102, ferroelectric film 103 and gate electrode 104 are stacked in this order on the substrate 101. The ferroelectric film 103 is made of a metal oxide such as lead zirconate titanate (PZT) or bismuth strontium tantalate (SBT). The gate electrode 104 is made of a conductor like platinum (Pt). And the source/drain regions 105 and 106 are defined in the substrate 101 and located on right- and left-hand sides of the gate electrode 104. In this device, part of the substrate 101 under the SiO2 film 102 serves as a channel region 107.
In the structure shown in FIG. 8, the ferroelectric film 103 exhibits electric spontaneous polarization of one of the following two types. More specifically, the electric dipole moment in the film 103 is either upward or downward depending on the polarity of a voltage applied between the gate electrode 104 and substrate 101. As used herein, the xe2x80x9cupward electric dipole momentxe2x80x9d refers to the electric moment of electric dipoles showing positive polarity at their upper end, while the xe2x80x9cdownward electric dipole momentxe2x80x9d refers to the electric moment of electric dipoles showing positive polarity at their lower end. The ferroelectric film 103 also shows dielectric hysteresis. That is to say, even after the voltage applied is removed, the polarization of either type remains in the film 103. Thus, the film 103 exhibits one of these two different types of remnant polarization while zero voltage is applied to the gate electrode 104. As a result, the channel region 107 of the ferroelectric FET enters one of two different states with mutually different potential depths corresponding to these two different types of remnant polarization. On the other hand, the source-drain resistance of the ferroelectric FET changes with the potential depth in the channel region 107. Accordingly, it depends on the type of remnant polarization exhibited by the ferroelectric film 103 whether the source-drain resistance becomes relatively high or relatively low. And one of these two different states, corresponding to the high and low source-drain resistance values, respectively, is retained (or stored) so long as the ferroelectric film 103 keeps its remnant polarization. This is why a nonvolatile memory device is realized by a ferroelectric FET like this.
In a nonvolatile memory device using the known ferroelectric FET, one state assumed by the ferroelectric film 103 with the down remnant polarization is normally associated with data xe2x80x9c1xe2x80x9d. The other state assumed by the ferroelectric film 103 with the up remnant polarization is normally associated with data xe2x80x9c0xe2x80x9d. To create the down remnant polarization in the ferroelectric film 103, a positive voltage may be applied to the gate electrode 104 with the backside of the substrate 101 grounded, and then the voltage applied to the electrode 104 may be reset to the ground level, for example. The up remnant polarization can be created in the ferroelectric film 103 in a similar manner. Specifically, first, a negative voltage may be applied to the gate electrode 104 with the backside of the substrate 101 grounded, and then the voltage applied to the electrode 104 may be reset to the ground level, for example.
FIGS. 9A, 9B and 9C are energy band diagrams illustrating respective energy band states corresponding to down, up and almost zero remnant polarization exhibited by the ferroelectric film 103. Each of these diagrams is illustrated for a cross section passing the gate electrode 104, ferroelectric film 103, SiO2 film 102 and channel region 107. In the example illustrated in FIGS. 9A, 9B and 9C, the substrate 101 is a p-type silicon substrate, the source/drain regions 105 and 106 are n-type semiconductor regions, and the arrows indicate the polarization directions of the ferroelectric film 103.
To create the state shown in FIG. 9A, a voltage is applied to the gate electrode 104 so that the electrode 104 has a positive potential level with respect to the substrate 101. That is to say, a positive voltage is applied to the electrode 104. In this case, a potential difference produced between the electrode 104 and substrate 101 is allotted at a certain ratio to the ferroelectric and SiO2 films 103 and 102 located between the electrode 104 and substrate 101. Specifically, if the voltage applied to the electrode 104 is regulated in such a manner as to make the potential difference allotted to the ferroelectric film 103 greater than a polarization reversal voltage of the film 103, then the film 103 exhibits down polarization. Thereafter, when the voltage applied to the electrode 104 is removed to reset the electrode 104 to the ground level, the film 103 produces down remnant polarization as shown in FIG. 9A. While the remnant polarization is downward (i.e., in the data xe2x80x9c1xe2x80x9d state), an electric field, created between the lower and upper ends of the ferroelectric film 103 with positive and negative polarities, respectively, bends the energy bands of the ferroelectric film 103, SiO2 film 102 and channel region 107 as shown in FIG. 9A. In such a situation, part of the channel region 107 near the interface between the region 107 and SiO2 film 102 changes its conductivity type from p- into n-type. That is to say, negative ions are densely concentrated at that part of the channel region 107. As a result, a depletion layer expands to the deeper part of the substrate 101, and the potential level at that part near the Sixe2x80x94SiO2 interface becomes lower than the ground level. In other words, a so-called xe2x80x9cinversion layerxe2x80x9d is formed in that part of the channel region 107.
On the other hand, to create the state shown in FIG. 9B, another voltage is applied to the gate electrode 104 so that the electrode 104 has a negative potential level with respect to the substrate 101. That is to say, a negative voltage is applied to the electrode 104. In this case, the voltage applied to the electrode 104 is regulated in such a manner as to make the potential difference allotted to the ferroelectric film 103 greater than the polarization reversal voltage of the film 103. Thereafter, when the voltage applied to the electrode 104 is removed to reset the electrode 104 to the ground level, the film 103 produces up remnant polarization as shown in FIG. 9B. While the remnant polarization is upward (i.e., in the data xe2x80x9c0xe2x80x9d state), an electric field, created between the lower and upper ends of the ferroelectric film 103 with negative and positive polarities, respectively, bends the energy bands of the ferroelectric film 103, SiO2 film 102 and channel region 107 as shown in FIG. 9B. In such a situation, however, holes, or majority carriers, are densely concentrated in that part of the channel region 107 near the Sixe2x80x94SiO2 interface. Accordingly, no depletion layer is formed in the channel region and the potential level at the channel region 107 is substantially equal to the ground level.
As can be seen, the potential level at that part of the channel region 107 near the Sixe2x80x94SiO2 interface changes depending on the direction of the remnant polarization. Accordingly, if a potential difference is produced between the source/drain regions 105 and 106 as a pair of n-type semiconductor regions, the amount of current flowing between these regions 105 and 106 also changes with the remnant polarization direction. Specifically, in the data xe2x80x9c1xe2x80x9d state, in which the potential level at the channel region 107 is lower than the ground level, the inversion layer is formed in the channel region 107 and therefore, the source-drain resistance is relatively low (i.e., in ON state). As a result, a large amount of current flows between the source/drain regions 105 and 106. In contrast, in the data xe2x80x9c0xe2x80x9d state, in which the potential level at the channel region 107 is equal to the ground level, no inversion layer is formed in the channel region 107 and therefore, the source-drain resistance is relatively high (i.e., in OFF state). As a result, current hardly flows between the source/drain regions 105 and 106. In other words, by measuring the current flowing between the source/drain regions 105 and 106, it is possible to know, by the amount of the current measured, whether the ferroelectric FET is in the data xe2x80x9c1xe2x80x9d or data xe2x80x9c0xe2x80x9d state.
As can be seen, to read the data state of a ferroelectric FET, just a potential difference should be created between the source/drain regions 105 and 106 but no bias needs to be applied to the gate electrode 104 as a matter of principle. That is to say, the ON state of a ferroelectric FET corresponds to the depletion mode of an MOS transistor.
The known ferroelectric FET, however, has the following drawbacks.
FIG. 10 is a graph illustrating a relationship between the voltage Vg applied to the gate electrode 104 of a ferroelectric FET and the source-drain current Ids in accordance with the results of experiments we carried out. As shown in FIG. 10, in reading out data by removing the voltage that has been applied to the gate electrode 104, a difference xcex94I1 between currents flowing in the data xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d states is small. This is probably because when zero voltage is applied to the gate electrode 104, the inversion layer formed in the channel region 107 has just a low intensity as shown in FIG. 9A. Accordingly, if the polarization of the ferroelectric film 103 has been changed with time, it might be difficult to read out data accurately enough, or to tell the data xe2x80x9c0xe2x80x9d state from the data xe2x80x9c1xe2x80x9d state definitely.
The known ferroelectric FET also has another problem. Specifically, if data xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d is stored on the device for a long period of time, then the hysteresis loop shifts in either the positive or negative direction along the voltage axis to create polarization in the direction associated with the data stored much more easily. This is called an xe2x80x9cimprint degradationxe2x80x9d. When this failure occurs, the ferroelectric film 103, which has been kept in a particular polarization state for a long time, will have its coercive voltage much increased. As used herein, the xe2x80x9ccoercive voltagexe2x80x9d is a voltage that should be applied to switch one polarization state into the other. That is to say, if the coercive voltage has increased, then polarization in the direction corresponding to the long-stored data occurs easily, but polarization in the opposite direction hardly occurs. Once the xe2x80x9cimprint degradationxe2x80x9d happens after data xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d has been stored on the ferroelectric film 103 of the ferroelectric FET for a long time, the ferroelectric film 103 will have a remnant polarizability different from its initial value. Accordingly, if some data is read out after having been retained there for a long time, the data could have a signal level (or read current value) different from an initial signal level (or read current value).
An object of the present invention is providing a semiconductor memory device that also changes a potential level at the channel region of an FET by utilizing the hysteresis of a ferroelectric thin film, but still can read out even long-stored data accurately enough.
Another object of the present invention is providing a method for driving a semiconductor memory device of that type.
Still another object of the present invention is providing a method for fabricating a semiconductor memory device of that type.
An inventive semiconductor memory device includes a field effect transistor. The transistor includes: a semiconductor substrate; a ferroelectric film and a gate electrode stacked in this order over the substrate; and source/drain regions defined in the substrate and located on right- and left-hand sides of the gate electrode. The ferroelectric film exhibits a first or second type of polarization. The first type of polarization is created when a voltage is applied to the gate electrode so that the electrode has a positive potential level with respect to the substrate. The second type of polarization is created when another voltage is applied to the gate electrode so that the electrode has a negative potential level with respect to the substrate. Data in a first or second logical state is stored in the ferroelectric film. The first logical state is defined as a state in which one of the first and second types of polarization remains in the ferroelectric film to which zero voltage is being applied. The second logical state is defined as a state in which either the other type of polarization or there is almost no remnant polarization in the ferroelectric film to which the zero voltage is being applied.
In this semiconductor device, even if data in the second logical state, written on the ferroelectric film, is indefinite or if there is almost no remnant polarization in the ferroelectric film, data can be read out accurately with the first and second logical states distinguished definitely.
In one embodiment of the present invention, a bias voltage is preferably applied to the gate electrode in reading out data from the ferroelectric film. Then, it is possible to increase the difference between a read current flowing where data in the first logical state is stored in the ferroelectric film and a read current flowing where data in the second logical state is stored in the ferroelectric film. As a result, the read accuracy improves.
In this particular embodiment, as data is repeatedly read out with the bias voltage applied, a disturb phenomenon is observed. That is to say, the other type of polarization, remaining in the ferroelectric film, gradually decreases toward zero. Even so, in reading out data, the first logical state may be defined as a state in which a current, substantially equal in amount to a current that flowed when the one type of polarization was written, flows between the source/drain regions. And the second logical state may be defined as a state in which a current in a predetermined range flows between the source/drain regions. The range is limited by a current that flowed when the other type of polarization was written and a current that flowed when the other type of polarization reached almost zero. In such an embodiment, the degradation of read accuracy, usually caused by the disturb phenomenon, is suppressible.
Another inventive semiconductor memory device includes a field effect transistor. The transistor includes: a semiconductor substrate; a ferroelectric film and a gate electrode stacked in this order over the substrate; and source/drain regions defined in the substrate and located on right- and left-hand sides of the gate electrode. The ferroelectric film exhibits a first or second type of polarization. The first type of polarization is created when a voltage is applied to the gate electrode so that the electrode has a positive potential level with respect to the substrate. The second type of polarization is created when another voltage is applied to the gate electrode so that the electrode has a negative potential level with respect to the substrate. Data in a first or second logical state is stored in the ferroelectric film. The first logical state is defined as a state in which one of the first and second types of polarization remains in the ferroelectric film to which zero voltage is being applied. The second logical state is defined as a state in which there is almost no remnant polarization in the ferroelectric film to which the zero voltage is being applied.
In this semiconductor device, data in the second logical state represents a state in which almost no polarization remains from the very beginning due to the disturb phenomenon. Accordingly, in reading out data, a read current value, corresponding to the data in the second logical state, becomes substantially constant. Thus, it is possible to tell the data in the second logical state from data in the first logical state even more definitely. As a result, the data read accuracy improves noticeably.
In one embodiment of the present invention, data in the first logical state and data in the second logical state are preferably written on the ferroelectric film by applying voltages with mutually different absolute values to the gate electrode.
In another embodiment of the present invention, the transistor may further include: a gate insulating film deposited on the substrate; and an intermediate gate electrode formed on the gate insulating film. The ferroelectric film may be deposited on the intermediate gate electrode, and the gate electrode may be formed on the ferroelectric film. In writing data, the first or second type of polarization is allowed to remain in the ferroelectric film by regulating a voltage applied between the gate electrode and the intermediate gate electrode. In reading data, a bias voltage is applicable to the gate electrode by making the intermediate gate electrode floating. In such an embodiment, the same effects are attainable for a semiconductor memory device including, as a memory cell, a field effect transistor with an MFMIS structure.
In still another embodiment, the transistor may further include: a gate insulating film deposited on the substrate; a first intermediate gate electrode formed on the gate insulating film; and a second intermediate gate electrode, which is formed separately from, and is electrically connected to, the first intermediate gate electrode. The ferroelectric film may be deposited on the second intermediate gate electrode. The gate electrode may be formed on the ferroelectric film. In writing data, the first or second type of polarization is allowed to remain in the ferroelectric film by regulating a voltage applied between the gate electrode and the second intermediate gate electrode. In reading data, a bias voltage is applicable to the gate electrode by making the first and second intermediate gate electrodes floating. In such an embodiment, the same effects are attainable for a semiconductor memory device including, as a memory cell, a field effect transistor substantially having an MFIS structure.
An inventive driving method is applicable to a semiconductor memory device including a field effect transistor. The transistor includes: a semiconductor substrate; a ferroelectric film and a gate electrode stacked in this order over the substrate; and source/drain regions defined in the substrate and located on right- and left-hand sides of the gate electrode. The ferroelectric film exhibits a first or second type of polarization. The first type of polarization is created when a voltage is applied to the gate electrode so that the electrode has a positive potential level with respect to the substrate. The second type of polarization is created when another voltage is applied to the gate electrode so that the electrode has a negative potential level with respect to the substrate. Data in a first or second logical state is read out from the ferroelectric film. The first logical state is defined as a state in which one of the first and second types of polarization remains in the ferroelectric film to which zero voltage is being applied. The second logical state is defined as a state in which either the other type of polarization or there is almost no remnant polarization in the ferroelectric film to which the zero voltage is being applied.
According to the inventive driving method, even if data in the second logical state, written on the ferroelectric film, is indefinite or if there is almost no remnant polarization in the ferroelectric film, data can be read out accurately with the first and second logical states distinguished definitely.
In one embodiment of the present invention, a bias voltage is preferably applied to the gate electrode in reading out data from the ferroelectric film. Then, it is possible to increase the difference between a read current flowing where data in the first logical state is stored in the ferroelectric film and a read current flowing where data in the second logical state is stored in the ferroelectric film. As a result, the read accuracy improves.
In this particular embodiment, as data is repeatedly read out with the bias voltage applied, a disturb phenomenon likely occurs. That is to say, the other type of polarization, remaining in the ferroelectric film, gradually decreases toward zero. Even so, in reading out data, the first logical state may be defined as a state in which a current, substantially equal in amount to a current that flowed when the one type of polarization was written, flows between the source/drain regions. And the second logical state may be defined as a state in which a current in a predetermined range flows between the source/drain regions. The range is limited by a current that flowed when the other type of polarization was written and a current that flowed when the other type of polarization reached almost zero. In such an embodiment, the degradation of read accuracy, usually caused by the disturb phenomenon, is suppressible.
In still another embodiment, the bias voltage applied to the gate electrode preferably has such a value as maximizing a difference between a current flowing between the source/drain regions when the data stored in the ferroelectric film is in the first logical state and a current flowing between the source/drain regions when the data stored in the ferroelectric film is in the second logical state.
Another inventive driving method is applicable to a semiconductor memory device including a field effect transistor. The transistor includes: a semiconductor substrate; a ferroelectric film and a gate electrode stacked in this order over the substrate; and source/drain regions defined in the substrate and located on right- and left-hand sides of the gate electrode. The ferroelectric film exhibits a first or second type of polarization. The first type of polarization is created when a voltage is applied to the gate electrode so that the electrode has a positive potential level with respect to the substrate. The second type of polarization is created when another voltage is applied to the gate electrode so that the electrode has a negative potential level with respect to the substrate. Data in a first or second logical state is stored in the ferroelectric film. The first logical state is defined as a state in which one of the first and second types of polarization remains in the ferroelectric film to which zero voltage is being applied. The second logical state is defined as a state in which there is almost no remnant polarization in the ferroelectric film to which the zero voltage is being applied. In reading out data from the ferroelectric film, a bias voltage is applied to the gate electrode.
According to the inventive driving method, data in the second logical state represents a state in which almost no polarization remains from the very beginning due to the disturb phenomenon. Accordingly, in reading out data, a read current value, corresponding to the data in the second logical state, becomes substantially constant. Thus, it is possible to tell the data in the second logical state from data in the first logical state even more definitely. As a result, the data read accuracy improves noticeably.
In this particular embodiment, the voltage applied to the gate electrode when data in the first logical state is written on the ferroelectric film preferably has an absolute value different from that of the voltage applied to the gate electrode when data in the second logical state is written on the ferroelectric film. In such an embodiment, data in the second logical state can easily represent a state in which almost no polarization remains from the very beginning due to the disturb phenomenon.
In still another embodiment, the transistor may further include: a gate insulating film deposited on the substrate; and an intermediate gate electrode formed on the gate insulating film. The ferroelectric film may be deposited on the intermediate gate electrode. The gate electrode may be formed on the ferroelectric film. In writing data, a voltage may be applied between the gate electrode and the intermediate gate electrode. And in reading data, a bias voltage may be applied to the gate electrode by making the intermediate gate electrode floating. In such an embodiment, the same effects are attainable for a semiconductor memory device including, as a memory cell, a field effect transistor with an MFMIS structure.
In an alternative embodiment, the transistor may further include: a gate insulating film deposited on the substrate; a first intermediate gate electrode formed on the gate insulating film; and a second intermediate gate electrode, which is formed separately from, and is electrically connected to, the first intermediate gate electrode. The ferroelectric film may be deposited on the second intermediate gate electrode. The gate electrode may be formed on the ferroelectric film. In writing data, a voltage may be applied between the gate electrode and the second intermediate gate electrode. And in reading data, a bias voltage may be applied to the gate electrode by making the first and second intermediate gate electrodes floating. In such an embodiment, the same effects are attainable for a semiconductor memory device including, as a memory cell, a field effect transistor substantially having an MFMIS structure.
In still another embodiment, in writing data in the second logical state on the ferroelectric film, the bias voltage applied to the gate electrode may be so regulated as to make a voltage supplied to the ferroelectric film substantially equal to a coercive voltage of the ferroelectric film. In such an embodiment, the data can be written while defining, as the second logical state, a state in which there is almost no remnant polarization in the ferroelectric film.
In yet another embodiment, either after data has been written on the ferroelectric film or before data is read out from the ferroelectric film, the intermediate gate electrode may be once grounded and then made floating. In this manner, unnecessary charge is removable from the intermediate electrode, thus improving the read accuracy.
In yet another embodiment, in reading out data that has been written on the ferroelectric film, the voltage applied to the gate electrode is preferably so regulated as to make a voltage supplied to the ferroelectric film lower than a coercive voltage of the ferroelectric film.
An inventive method for fabricating a semiconductor memory device includes the step of a) forming a memory cell including a field effect transistor. The transistor includes: a semiconductor substrate; a ferroelectric film and a gate electrode stacked in this order over the substrate; and source/drain regions defined in the substrate and located on right- and left-hand sides of the gate electrode. The ferroelectric film exhibits a first or second type of polarization. The first type of polarization is created when a voltage is applied to the gate electrode so that the electrode has a positive potential level with respect to the substrate. The second type of polarization is created when another voltage is applied to the gate electrode so that the electrode has a negative potential level with respect to the substrate. The method further includes the step of b) applying a voltage, which has the same polarity as a voltage applied for reading out data, to the ferroelectric film and then removing the former voltage so that the first type of polarization remains in the ferroelectric film. And the method further includes the step of c) heating the ferroelectric film for a predetermined period of time, thereby shifting hysteresis properties of the ferroelectric film in such a direction that a coercive voltage, needed to reverse the type of polarization from the first into the second, increases and making the hysteresis properties of the ferroelectric film asymmetric.
According to the inventive fabrication method, the polarization state of the ferroelectric film can be shifted toward the first logical state in advance. Thus, in reading out data, it is easier to tell data in the first logical state from data in the second logical state.
In one embodiment of the present invention, the method may further include the step of erasing the first type of polarization remaining in the ferroelectric film after the step b) has been performed.